entity FullAdder is
  port (A, B, CIN: in bit; SUM, COUT: out bit);
end entity FullAdder;
 
architecture LogicOperation of FullAdder is
begin
  SUM <= (A xor B) xor CIN;
  COUT <= ((A xor B) and CIN) or (A and B);
end architecture LogicOperation;
 
entity 4BitFullAdder is
  port (A1, A2, A3, A4, B1, B2, B3, B4, C0: in bit; S1, S2, S3, S4, C4: out bit);
end entity 4BitFullAdder;
 
architecture LogicOperation of 4BitFullAdder is
  component FullAdder is
    port (A, B, CIN: in bit; SUM, COUT: out bit);
  end component FullAdder;
  signal Cl, C2, C3: bit;
 
begin
FA1: FullAdder port map (A =7 A1, B =7 B1, CIN =7 C0, SUM =7 S1, COUT =7 Cl);
FA2: FullAdder port map (A =7 A2, B =7 B2, CIN =7 C1, SUM =7 S2, COUT =7 C2);
FA3: FullAdder port map (A =7 A3, B =7 B3, CIN =7 C2, SUM =7 S3, COUT =7 C3);
FA4: FullAdder port map (A =7 A4, B =7 B4, CIN =7 C3, SUM =7 S4, COUT =7 C4);
 
end architecture LogicOperation;